Cadence also provides a new aging model for device degradation in advanced nodes with FinFET transistors. In this release, Cadence is enhancing aging analysis to include the effects that accelerate device wear-out including temperature and process variation. Dynamic electro-thermal simulation allows designers to simulate the on-chip temperature rise and validate the operation of over temperature protection circuits.Īdvanced Aging Analysis Predicts Product Wear-outĬadence is the recognized leader in aging analysis, providing technologies like RelXpert and AgeMOS to analyze the device degradation due to electrical stress. The combination of high-power dissipation in a high-temperature environment can result in thermal overstress that can result in failure during normal operation. In addition, these components need to operate in hostile environments under the hood of an automobile. For automotive designers, for example, actual usage results in significant temperature rise during normal operation due to on-chip losses and power dissipated in the switches. In this release, Cadence is introducing a dynamic electro-thermal simulation engine.
We verified the solution and plan to adopt it for use in our production flow.”Įlectro-Thermal Analysis Prevents Thermal Overstress
“We tested the Legato Reliability Solution and were able to accelerate the simulation time by a factor of more than 100. “Analog defect simulation is becoming very important for us to meet our customers’ expectations,” stated Dieter Härle, project manager, Infineon Austria. Customer experience with the tool indicates that it accelerates defect simulation by more than 100X. It can also be used to optimize wafer test, reducing the number of tests required to achieve the target defect coverage by eliminating over-testing and potentially reducing the number of tests up to 30 percent. Defect-oriented testing allows designers to evaluate the ability to eliminate die with manufacturing defects and resulting test escapes that cause field failures. In this release, Cadence introduces a simulation engine to enable a new test methodology for analog ICs-defect-oriented testing-that expands the capabilities of test far beyond what is traditionally achieved by just performing functional and parametric tests. Our new Legato Reliability solution enables designers to answer these critical questions much earlier in the design process.”Īnalog Defect Analysis Reduces Test Cost and Reduces Test Escapes
“Designers are faced with the challenge of designing across the entire lifecycle, including eliminating the test escapes that become field failures early in the life cycle, preventing thermal overstress from operating in extreme conditions like under the hood of a car, and designing for 15 years or more of operating lifetime.
#Cadence virtuoso layout 100 pins simulator#
The Legato Reliability Solution provides analog designers with the tools they need to manage their design’s reliability throughout the product lifecycle, from initial test through active life through aging.īased on the golden, trusted Cadence Spectre ® Accelerated Parallel Simulator and the Cadence Virtuoso ® custom IC design platform, the Legato Reliability Solution integrates capabilities into an intuitive cockpit to address the reliability concerns of the three phases of the product lifecycle:
#Cadence virtuoso layout 100 pins software#
(NASDAQ: CDNS) today introduced the Cadence ® Legato™ Reliability Solution, the industry’s first software product that meets the challenges of designing high-reliability analog and mixed-signal integrated circuits (ICs) for automotive, medical, industrial, and aerospace and defense applications. Addresses reliability challenges across the product lifecycle for automotive, medical, industrial, aerospace and defense applicationsĬadence Design Systems, Inc.